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rt7247c ? ds7247c-02 september 2012 www.richtek.com 1 copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? applications z wireless ap/router z set-top-box z industrial and commercial low power systems z lcd monitors and tvs z green electronics/appliances z point of load regulation of high-performance dsps 2a, 18v, 800khz synchronous step-down converter general description the rt7247c is a high efficiency, monolithic synchronous step-down dc/dc converter that can deliver up to 2a output current from a 4.5v to 18v input supply. the rt7247c's current mode architecture and external compensation allow the transient response to be optimized over a wide input range and loads. cycle-by- cycle current limit provides protection against shorted outputs, and soft-start eliminates input current surge during start-up. the rt7247c also provides under voltage protection and thermal shutdown protection. the low current (<3 a) shutdown mode provides output disconnection, enabling easy power management in battery-powered systems. the rt7247c is available in an sop-8 (exposed pad) package. features z z z z z 1.5% high accuracy reference voltage z z z z z 4.5v to 18v input voltage range z z z z z 2a output current z z z z z integrated n-mosfet switches z z z z z current mode control z z z z z fixed frequency operation : 800khz z z z z z output adjustable from 0.8v to 12v z z z z z stable with low esr ceramic output capacitors z z z z z up to 95% efficiency z z z z z programmable soft-start z z z z z cycle-by-cycle over current limit z z z z z input under voltage lockout z z z z z output under voltage protection z z z z z thermal shutdown protection z z z z z rohs compliant and halogen free marking information rt7247chgsp : product number ymdnn : date code simplified application circuit vin en gnd boot fb sw l r1 r2 v out v in rt7247c ss c ss comp c c r c c p c boot c in c out chip enable rt7247ch gspymdnn
rt7247c ? ds7247c-02 september 2012 www.richtek.com 2 copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? functional pin description pin no. pin name pin function 1 boot bootstrap for high side gate driver. connect a 0.1 f or greater ceramic capacitor from boot to sw pins. 2 vin power input. the input voltage range is fr om 4.5v to 18v. must bypass with a suitable large ceramic capacitor. 3 sw switch node. connect this pin to an external l-c filter. 4, 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 5 fb feedback input. it is used to regulate the output of the converter to a set value via an external resistive voltage divider. 6 comp compensation node. comp is used to compensate the regulation control loop. connect a series rc network from comp to gnd. in some cases, an additional capacitor from comp to gnd is required. 7 en enable input. a logic high enables the converter; a logic low forces the ic into shutdown mode reducing the supply current to less than 3 a. 8 ss soft-start control input. ss controls the soft-start period. connect a capacitor from ss to gnd to set the soft-start period. a 0.1 f capacitor sets the soft-start period to 13.5ms. ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pin configurations (top view) sop-8 (exposed pad) boot vin sw gnd ss en fb comp gnd 2 3 4 5 6 7 8 9 package type sp : sop-8 (exposed pad-option 2) rt7247c lead plating system g : green (halogen free and pb free) h : uvp hiccup
rt7247c ? ds7247c-02 september 2012 www.richtek.com 3 copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? function block diagram operation internal regulator provide internal power for logic control and switch gate drivers. shutdown comparator activate internal regulator once en input level is higher than the target level. force ic to enter shutdown mode when the en input level is lower than 0.4v. lockout comparator activate the current comparator, release lock-out logic, and enable the switches as en input level is higher than lockout threshold voltage. otherwise, the switches still lock out. oscillator the oscillator provides internal clock and controls the converter's switching frequency. foldback control dynamically adjust the internal clock. it provides a slower frequency as a lower fb voltage. uv comparator as fb voltage is lower than the uv voltage, it will activate a uv protect scheme. error amplifier the output voltage comp of the error amplifier is adjusted by comparing fb signal with the internal reference voltage and ss signal. current sense amplifier r sense detects the peak current of the high side switch. this signal is amplified by the current sense amplifier and added with a slope compensation signal. then, it controls the switches by comparing this signal with the comp voltage. v a + - + - + - uv comparator oscillator foldback control 0.4v internal regulator + - 1.8v shutdown comparator current sense amplifier boot vin gnd sw fb en comp v a v cc 6a slope comp current comparator + - ea 0.8v s r q q ss + - 1.2v lockout comparator v cc + 130m 150m 5k r sense
rt7247c 4 ds7247c-02 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. electrical characteristics (v in = 12v, t a = 25 c, unless otherwise specified) absolute maximum ratings (note 1) z supply input v oltage, vin ----------------------------------------------------------------------------------------- ? 0.3v to 20v z switch voltage, sw ------------------------------------------------------------------------------------------------ ? 0.3v to (v in + 0.3v) z v boot ? v sw ---------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z other pin s v oltage ------------------------------------------------------------------------------------------------- ? 0.3v to 20v z power dissipation, p d @ t a = 25 c sop-8 (exposed pad) --------------------------------------------------------------------------------------------- 1.333w z package thermal resistance (note 2) sop-8 (exposed pad), ja ---------------------------------------------------------------------------------------- 75 c/w sop-8 (exposed pad), jc --------------------------------------------------------------------------------------- 15 c/w z lead temperature (soldering, 10 sec.) ------------------------------------ ------------------------------------- 260 c z junction temperature ----------------------------------------------------------------------------------------------- 150 c z storage temperature range -------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) ---------------------------------------------------------------------------------------- 2kv recommended operating conditions (note 4) z supply input voltage, vin ----------------------------------------------------------------------------------------- 4.5v to 18v z junction temperature range -------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------- ? 40 c to 85 c parameter symbol test conditions min typ max unit shutdown supply current v en = 0v -- 0.5 3 a supply current v en = 3v, v fb = 0.9v -- 0.8 1.2 ma reference voltage v ref 4.5v v in 18v 0.788 0.8 0.812 v error amplifier transconductance g ea i c = 10 a -- 940 -- a/v high side switch on-resistance r ds(on)1 -- 150 -- m low side switch on-resistance r ds(on)2 -- 130 -- m high side switch leakage current v en = 0v, v sw = 0v -- 0 10 a upper switch current limit min. duty cycle, v boot ? v sw = 4.8v -- 5.1 -- a comp to current sense transconductance g cs -- 3.7 -- a/v oscillation frequency f osc1 -- 800 -- khz short circuit oscillation frequency f osc2 v fb = 0v -- 270 -- khz maximum duty cycle d max v fb = 0.7v -- 84 -- % minimum on-time t on -- 100 -- ns
rt7247c 5 ds7247c-02 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. parameter symbol test conditions min typ max unit logic-high v ih 2 -- 18 en input threshold voltage logic-low v il -- -- 0.4 v input under voltage lockout threshold v uvlo v in rising 3.8 4.2 4.5 v input under voltage lockout hysteresis v uvlo -- 320 -- mv soft-start current i ss v ss = 0v -- 6 -- a soft-start period t ss c ss = 0.1 f -- 13.5 -- ms thermal shutdown t sd -- 150 -- c note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
rt7247c 6 ds7247c-02 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. typical application circuit v out (v) r1 (k ) r2 (k ) r c (k ) c c (nf) l ( h) c out ( f) 8 27 3 40 3.3 15 22 x 2 5 62 11.8 25 3.3 10 22 x 2 3.3 75 24 17 3.3 6.8 22 x 2 2.5 25.5 12 13 3.3 4.7 22 x 2 1.5 10.5 12 7 3.3 3.6 22 x 2 1.2 12 24 6 3.3 2 22 x 2 1 3 12 5 3.3 2 22 x 2 table 1. suggested components selection vin en gnd boot fb sw 7 5 2 3 1 l 6.8h 0.1f 22f x 2 r1 75k r2 24k v out 3.3v 10f x 2 v in 4.5v to 18v rt7247c ss 8 c ss comp c c 3.3nf r c 17k c p open 6 4, 9 (exposed pad) c boot c in 0.1f c out chip enable
rt7247c 7 ds7247c-02 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. output voltage vs. output current 3.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 output current (a) output voltage (v) v in = 12v v in = 17v v out = 3.3v typical operating characteristics switching frequency vs. temperature 720 730 740 750 760 770 780 790 800 -50 -25 0 25 50 75 100 125 temperature (c) switching frequency (khz) 1 v in = 17v v in = 12v v in = 4.5v v out = 3.3v, i out = 0a output voltage vs. temperature 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 -50-25 0 25 50 75100125 temperature (c) output voltage (v) v in = 12v, v out = 3.3v switching frequency vs. input voltage 740 750 760 770 780 790 800 810 820 4 6 8 1012141618 input voltage (v) switcing frequency (khz) 1 v in = 4.5v to 17v, v out = 3.3v, i out = 0a efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 00.511.52 output current (a) efficiency (%) v in = 4.5v v in = 12v v in = 17v v out = 3.3v output voltage vs. input voltage 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 4 6 8 1012141618 input voltage (v) output voltage (v) v in = 4.5v to 17v
rt7247c 8 ds7247c-02 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. time (500ns/div) output ripple voltage v out (5mv/div) v sw (10v/div) v in = 12v, v out = 3.3v, i out = 1a i l (1a/div) uvlo threshold vs. temperature 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 -50-25 0 25 50 75100125 temperature (c) uvlo threshold (v) rising falling output current limit vs. temperature 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -50-25 0 25 50 75100125 temperature (c) output current limit (a ) v in = 12v, v out = 3.3v time (500ns/div) output ripple voltage v out (5mv/div) v sw (10v/div) v in = 12v, v out = 3.3v, i out = 2a i l (1a/div) time (100 s/div) load transient response v out (200mv/div) i out (1a/div) v in = 12v, v out = 3.3v, i out = 0a to 2a time (100 s/div) load transient response v out (200mv/div) i out (1a/div) v in = 12v, v out = 3.3v, i out = 1a to 2a
rt7247c 9 ds7247c-02 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. time (10ms/div) power off from en v in = 12v, v out = 3.3v, i out = 2a v out (2v/div) v en (5v/div) i out (2a/div) time (10ms/div) power on from en v in = 12v, v out = 3.3v, i out = 2a v out (2v/div) v en (5v/div) i out (2a/div) time (10ms/div) power on from vin v in = 12v, v out = 3.3v, i out = 2a v out (2v/div) v in (5v/div) i out (2a/div) time (25ms/div) power off from vin v in = 12v, v out = 3.3v, i out = 2a v out (2v/div) v in (5v/div) i out (2a/div)
rt7247c 10 ds7247c-02 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. application information output voltage setting the resistive divider allows the fb pin to sense the output voltage as shown in figure 1. figure 1. output voltage setting the output voltage is set by an external resistive voltage divider according to the following equation : out ref r1 v = v 1 r2 ?? + ?? ?? where v ref is the reference voltage (0.8v typ.). external bootstrap diode connect a 0.1 f low esr ceramic capacitor between the boot pin and sw pin. this capacitor provides the gate driver voltage for the high side mosfet. it is recommended to add an external bootstrap diode between an external 5v and boot pin for efficiency improvement when input voltage is lower than 5.5v or duty ratio is higher than 65% .the bootstrap diode can be a low cost one such as in4148 or bat54. the external 5v can be a 5v fixed input from system or a 5v output of the rt7247c. note that the external boot voltage must be lower than 5.5v figure 2. external bootstrap diode soft-start the rt7247c provides soft-start function. the soft-start function is used to prevent large inrush current while converter is being powered-up. the soft-start timing can be programmed by the external capacitor between ss and gnd. an internal current source i ss (6 a) charges an external capacitor to build a soft-start ramp voltage. the v fb voltage will track the internal ramp voltage during soft- start interval. the typical soft-start time is calculated as follows : an external mosfet can be added to implement digital control on the en pin when no system voltage above 2v is available, as shown in figure 4. in this case, a 100k pull-up resistor, r en , is connected between v in and the en pin. mosfet q1 will be under logic control to pull down the en pin. chip enable operation the en pin is the chip enable input. pulling the en pin low (<0.4v) will shut down the device. during shutdown mode, the rt7247c quiescent current drops to lower than 3 a. driving the en pin high (>2v, <18v) will turn on the device again. for external timing control, the en pin can also be externally pulled high by adding a r en resistor and c en capacitor from the vin pin (see figure 3). ss ss ss ss 0.8 c soft-start time t = , if c capacitor i 0.8 0.1 is 0.1 f, then soft-start time = 13.5ms 6 P figure 3. enable timing control figure 4. digital enable control circuit rt7247c gnd fb r1 r2 v out sw boot 5v rt7247c 0.1f rt7247c en gnd v in r en c en en rt7247c en gnd 100k v in r en q1 en
rt7247c 11 ds7247c-02 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? under voltage protection hiccup mode for the rt7247c, it provides hiccup mode under voltage protection (uvp). when the v fb voltage drops below 0.4v, the uvp function will be triggered to shut down switching operation. if the uvp condition remains for a period, the rt7247c will retry automatically. when the uvp condition is removed, the converter will resume operation. the uvp is disabled during soft-start period. having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. high frequency with small ripple current can achieve the highest efficiency operation. however, it requires a large inductor to achieve this goal. for the ripple current selection, the val ue of i l = 0.24(i max ) will be a reasonable starting point. the large st ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : table 2. suggested inductors for typical application circuit component supplier series dimensions (mm) tdk vlf10045 10 x 9.7 x 4.5 tdk slf12565 12.5 x 12.5 x 6.5 taiyo yuden nr8040 8 x 8 x 4 out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? the inductor's current rating (caused a 40 c temperature rising from 25 c ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. please see table 2 for the inductor selection reference. figure 5. hiccup mode under voltage protection over temperature protection the rt7247c features an over temperature protection (otp) circuitry to prevent from overheating due to excessive power dissipation. the otp will shut down switching operation when junction temperature exceeds 150 c. once the junction temperature cools down by approximately 20 c, the converter will resume operation. to maintain continuous operation, the maximum junction temperature should be lower than 125 c. inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current i l increases with higher v in and decreases with higher inductance. time (50ms/div) hiccup mode v out (2v/div) i lx (2a/div) i out = short out in rms out(max) in out v v i = i 1 vv ? c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the high side mosfet. to prevent large ripple current, a low esr input capacitor sized for the maximum rms current should be used. the approximate rms current is given : this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for the input capacitor, two 10 f low esr ceramic capacitors are suggested. for the
rt7247c 12 ds7247c-02 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. figure 7. derating curve of maximum power dissipation 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0255075100125 ambient temperature (c) power dissipation (w) copper area 70mm 2 50mm 2 30mm 2 10mm 2 min.layout four-layer pcb out l out 1 viesr 8fc ?? ?? + ?? ?? the output ripple will be the highest at the maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirement. higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. thermal considerations for continuous operation, do not exceed the maximum operation junction temperature 125 c. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature , t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ja is layout dependent. for sop-8 (exposed pad) package, the thermal resistance suggested capacitor, please refer to table 3 for more details. the selection of c out is determined by the required esr to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for cout selection to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : ja is 75 c/w on the standard jedec 51-7 four-layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (75 c/w) = 1.333w (min.copper area pcb layout) p d(max) = (125 c ? 25 c) / (49 c/w) = 2.04w (70mm 2 copper area pcb layout) the thermal resistance ja of sop-8 (exposed pad) is determined by the package architecture design and the pcb layout design. however, the package architecture design had been designed. if possible, it's useful to increase thermal performance by the pcb layout copper design. the thermal resistance ja can be decreased by adding copper area under the exposed pad of sop-8 (exposed pad) package. as shown in figure 6, the amount of copper area to which the sop-8 (exposed pad) is mounted affects thermal performance. when mounted to the standard sop-8 (exposed pad) pad (figure 6.a), ja is 75 c/w. adding copper area of pad under the sop-8 (exposed pad) (figure 6.b) reduces the ja to 64 c/w. even further, increasing the copper area of pad to 70mm 2 (figure 6.e) reduces the ja to 49 c/w. the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 7 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed.
rt7247c 13 ds7247c-02 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. (a) copper area = (2.3 x 2.3) mm 2 , ja = 75 c/w (b) copper area = 10mm 2 , ja = 64 c/w (c) copper area = 30mm 2 , ja = 54 c/w (d) copper area = 50mm 2 , ja = 51 c/w (e) copper area = 70mm 2 , ja = 49 c/w figure 6. thermal resistance vs. copper area layout design layout consideration follow the pcb layout guidelines for optimal performance of the rt7247c. ` keep the traces of the main current paths as short and wide as possible. ` put the input capacitor as close as possible to the device pins (vin and gnd). ` sw node is with high frequency voltage swing and should be kept at small area. keep analog components away from the sw node to prevent stray capacitive noise pick-up. ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the rt7247c. ` an example of pcb layout guide is shown in figure 8 for reference.
rt7247c 14 ds7247c-02 september 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. figure 8. pcb layout guide table 3. suggested capacitors for c in and c out location component supplier part no. capacitance ( f) case size c in murata GRM31CR61E106K 10 1206 c in tdk c3225x5r1e106k 10 1206 c in taiyo yud en tmk316bj106ml 10 1206 c out murata grm31cr60j476m 47 1206 c out tdk c3225x5r0j476m 47 1210 c out murata grm32er71c226m 22 1210 c out tdk c3225x5r1c22m 22 1210 v in v out gnd c in gnd c p c c r c sw v out c out l r1 r2 input capacitor must be placed as close to the ic as possible. sw node is with high fre quency voltage swing and should be kept at small area. k eep analog components away from the sw node to prevent stray capacitive noise pick-up the feedback components must be connected as close to the device as possible. boot vin sw gnd ss en fb comp gnd 2 3 4 5 6 7 8 9 c ss gnd v in r en c boot
rt7247c 15 ds7247c-02 september 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138

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